Please Scroll down to read Book's details, context and topics:
This document contains my personal notes in the form of manuscripts from self-study and class lectures when I was taking the Computer Architecture class taught by Dr. Suboh Suboh at the University of Central Florida. This document consists of handmade annotations that I did myself about the subject, it contains common and fundamental knowledge about the field. These notes represent a distilled version of what I deemed significant and readily available in literature.
The purpose of this document is to provide students with an additional resource for their learning, fostering curiosity and aiding in self-study. Certain images, diagrams and definitions included in my notes are sourced from the books: “Computer Architecture, A Quantitative Approach by John L, Hennessy, David A. Patterson, 6 th edition” and “Computer Organization and Design, The Hardware – Software Interphase by David A. Patterson and John L. Hennessy 5th edition”.
Computer Architecture is an elective class for general track electrical engineers, especially recommended for students that have a tendency for career paths in digital systems, memory management and computer design. Please do not use this information for graded assignments of any kind. This document is solely for self-study and enjoyment.
Some of the relevant topics that can be found in this document are:
• Instruction Set Architecture (ISA)
• Micro-Architecture
• Old ISA Styles (Accumulator, Stack, Mem to Mem)
• Newer ISA Styles (Reg to mem and Reg to Reg)
• Addressing Modes
• Memory Indirect Mode
• Autodetect Mode
• Scaled Addressing Mode
• PC – Relative Addressing Mode
• Common Data Types
• Operations in the Instruction Set
• Virtual Memory
• Private Virtual Address
• Write- Through and Write-Back
• Page Tables
• Mapping pages to Storage
• Virtual Memory Applications
• Virtual Memory Implementation
• Linear Table
• Inverted Page Table
• Multi-Level Page Table
• Replacement Policies
• Data-Path
• Pipelining
• Cache memory (Multilevel Cache)
• Cache vs TLB
• Associativity concepts
• Multilevel Cache
• MSI Protocol (Modified, Shared, Invalid)
• Two Levels of Control
• Hazards
• Smith n-bit counter predictor
• G-Select
• AMAT (Memory Access Time)
• Multiple Issue CPU
• More Related Topics